itkpix1.hpp

#define REG_LIST_ITKPIX1(f) \
  f(PIX_PORTAL) \
  f(REGION_COL) \
  f(REGION_ROW) \
  f(PIX_MODE) \
  f(PIX_DEFAULT_CONFIG) \
  f(PIX_DEFAULT_CONFIG_B) \
  f(GCR_DEFAULT_CONFIG) \
  f(GCR_DEFAULT_CONFIG_B) \
  f(DAC_PREAMP_L_DIFF) \
  f(DAC_PREAMP_R_DIFF) \
  f(DAC_PREAMP_TL_DIFF) \
  f(DAC_PREAMP_TR_DIFF) \
  f(DAC_PREAMP_T_DIFF) \
  f(DAC_PREAMP_M_DIFF) \
  f(DAC_PRECOMP_DIFF) \
  f(DAC_COMP_DIFF) \
  f(DAC_VFF_DIFF) \
  f(DAC_TH1_L_DIFF) \
  f(DAC_TH1_R_DIFF) \
  f(DAC_TH1_M_DIFF) \
  f(DAC_TH2_DIFF) \
  f(DAC_LCC_DIFF) \
  f(DAC_PREAMP_L_LIN) \
  f(DAC_PREAMP_R_LIN) \
  f(DAC_PREAMP_TL_LIN) \
  f(DAC_PREAMP_TR_LIN) \
  f(DAC_PREAMP_T_LIN) \
  f(DAC_PREAMP_M_LIN) \
  f(DAC_FC_LIN) \
  f(DAC_KRUM_CURR_LIN) \
  f(DAC_REF_KRUM_LIN) \
  f(DAC_COMP_LIN) \
  f(DAC_COMP_TA_LIN) \
  f(DAC_GDAC_L_LIN) \
  f(DAC_GDAC_R_LIN) \
  f(DAC_GDAC_M_LIN) \
  f(DAC_LDAC_LIN) \
  f(LEAKAGE_FEEDBACK) \
  f(VOLTAGE_TRIM) \
  f(EnCoreCol_3) \
  f(EnCoreCol_2) \
  f(EnCoreCol_1) \
  f(EnCoreCol_0) \
  f(EnCoreColumnReset_3) \
  f(EnCoreColumnReset_2) \
  f(EnCoreColumnReset_1) \
  f(EnCoreColumnReset_0) \
  f(TriggerConfig) \
  f(SelfTriggerConfig_1) \
  f(SelfTriggerConfig_0) \
  f(HitOrPatternLUT) \
  f(ReadTriggerConfig) \
  f(TruncTimeoutConf) \
  f(CalibrationConfig) \
  f(CLK_DATA_FINE_DELAY) \
  f(VCAL_HIGH) \
  f(VCAL_MED) \
  f(MEAS_CAP) \
  f(CdrConf) \
  f(ChSyncConf) \
  f(GlobalPulseConf) \
  f(GlobalPulseWidth) \
  f(ServiceDataConf) \
  f(ToTConfig) \
  f(PrecisionToTEnable_3) \
  f(PrecisionToTEnable_2) \
  f(PrecisionToTEnable_1) \
  f(PrecisionToTEnable_0) \
  f(DataMerging) \
  f(DataMergingMux) \
  f(EnCoreColumnCalib_3) \
  f(EnCoreColumnCalib_2) \
  f(EnCoreColumnCalib_1) \
  f(EnCoreColumnCalib_0) \
  f(DataConcentratorConf) \
  f(CoreColEncoderConf) \
  f(EvenMask) \
  f(OddMask) \
  f(EfusesConfig) \
  f(EfusesWriteData1) \
  f(EfusesWriteData0) \
  f(AuroraConfig) \
  f(AURORA_CB_CONFIG1) \
  f(AURORA_CB_CONFIG0) \
  f(AURORA_INIT_WAIT) \
  f(OUTPUT_PAD_CONFIG) \
  f(GP_CMOS_ROUTE) \
  f(GP_LVDS_ROUTE_1) \
  f(GP_LVDS_ROUTE_0) \
  f(DAC_CP_CDR) \
  f(DAC_CP_FD_CDR) \
  f(DAC_CP_BUFF_CDR) \
  f(DAC_VCO_CDR) \
  f(DAC_VCOBUFF_CDR) \
  f(SER_SEL_OUT) \
  f(CML_CONFIG) \
  f(DAC_CML_BIAS_2) \
  f(DAC_CML_BIAS_1) \
  f(DAC_CML_BIAS_0) \
  f(MonitorConfig) \
  f(ErrWngMask) \
  f(MON_SENS_SLDO) \
  f(MON_SENS_ACB) \
  f(MON_ADC) \
  f(DAC_NTC) \
  f(HITOR_MASK_3) \
  f(HITOR_MASK_2) \
  f(HITOR_MASK_1) \
  f(HITOR_MASK_0) \
  f(AutoRead0) \
  f(AutoRead1) \
  f(AutoRead2) \
  f(AutoRead3) \
  f(AutoRead4) \
  f(AutoRead5) \
  f(AutoRead6) \
  f(AutoRead7) \
  f(RingOscConfig) \
  f(RingOscRoute)