fldlist_hcc1.hpp

#define FLD_LIST_SEP(f, s) \
  f(HPR_State_SEU)s \
  f(HPR_Counter_SEU)s \
  f(Reg48_SEU)s \
  f(Reg47_SEU)s \
  f(Reg46_SEU)s \
  f(Reg45_SEU)s \
  f(Reg44_SEU)s \
  f(Reg43_SEU)s \
  f(Reg42_SEU)s \
  f(Reg41_SEU)s \
  f(Reg40_SEU)s \
  f(Reg39_SEU)s \
  f(Reg38_SEU)s \
  f(Reg35_SEU)s \
  f(Reg34_SEU)s \
  f(Reg33_SEU)s \
  f(Reg32_SEU)s \
  f(Reg17_SEU)s \
  f(IC10_LP_UCE)s \
  f(IC9_LP_UCE)s \
  f(IC8_LP_UCE)s \
  f(IC7_LP_UCE)s \
  f(IC6_LP_UCE)s \
  f(IC5_LP_UCE)s \
  f(IC4_LP_UCE)s \
  f(IC3_LP_UCE)s \
  f(IC2_LP_UCE)s \
  f(IC1_LP_UCE)s \
  f(IC0_LP_UCE)s \
  f(IC10_LP_CE)s \
  f(IC9_LP_CE)s \
  f(IC8_LP_CE)s \
  f(IC7_LP_CE)s \
  f(IC6_LP_CE)s \
  f(IC5_LP_CE)s \
  f(IC4_LP_CE)s \
  f(IC3_LP_CE)s \
  f(IC2_LP_CE)s \
  f(IC1_LP_CE)s \
  f(IC0_LP_CE)s \
  f(frame_raw_lcb)s \
  f(frame_raw_R3L1)s \
  f(errcount_lcb)s \
  f(errcount_R3L1)s \
  f(ana_set)s \
  f(ADCval)s \
  f(Status_constant)s \
  f(prlp_sending)s \
  f(HCCStar_Version)s \
  f(GPI1)s \
  f(GPI0)s \
  f(ICsramOcc_Ch10)s \
  f(LP_IC_Full)s \
  f(ICsramOcc_Ch9)s \
  f(ICsramOcc_Ch8)s \
  f(IC_ABCoutstanding_Ch10)s \
  f(IC_ABCoutstanding_Ch9)s \
  f(IC_ABCoutstanding_Ch8)s \
  f(IC_ABCoutstanding_Ch7)s \
  f(IC_ABCoutstanding_Ch6)s \
  f(IC_ABCoutstanding_Ch5)s \
  f(IC_ABCoutstanding_Ch4)s \
  f(IC_ABCoutstanding_Ch3)s \
  f(IC_ABCoutstanding_Ch2)s \
  f(IC_ABCoutstanding_Ch1)s \
  f(IC_ABCoutstanding_Ch0)s \
  f(ICsramOcc_Ch7)s \
  f(ICsramOcc_Ch6)s \
  f(ICsramOcc_Ch5)s \
  f(ICsramOcc_Ch4)s \
  f(ICsramOcc_Ch3)s \
  f(ICsramOcc_Ch2)s \
  f(ICsramOcc_Ch1)s \
  f(ICsramOcc_Ch0)s \
  f(pr_rr_occ)s \
  f(lp_rr_occ)s \
  f(lcb_frame_raw)s \
  f(lcb_scmd_errcount)s \
  f(lcb_scmd_err)s \
  f(R3L1_errcount_ovfl)s \
  f(ePllInstantLock)s \
  f(k2_pending)s \
  f(lcb_errcount_ovfl)s \
  f(lcb_decode_err)s \
  f(lcb_locked)s \
  f(R3L1_locked)s \
  f(R3L1_errcount_clr)s \
  f(lcb_errcount_clr)s \
  f(eFuseL)s \
  f(TestHPR)s \
  f(StopHPR)s \
  f(Comm_id)s \
  f(Fuse_ID)s \
  f(lcba_delay160)s \
  f(FD_RCLK_fineDelay)s \
  f(FD_LCBa_fineDelay)s \
  f(CFD_PRLP_coarseDelay)s \
  f(CFD_PRLP_fineDelay)s \
  f(CFD_BC_coarseDelay)s \
  f(CFD_BC_fineDelay)s \
  f(FD_DataIn7_fineDelay)s \
  f(FD_DataIn6_fineDelay)s \
  f(FD_DataIn5_fineDelay)s \
  f(FD_DataIn4_fineDelay)s \
  f(FD_DataIn3_fineDelay)s \
  f(FD_DataIn2_fineDelay)s \
  f(FD_DataIn1_fineDelay)s \
  f(FD_DataIn0_fineDelay)s \
  f(FD_DataIn10_fineDelay)s \
  f(FD_DataIn9_fineDelay)s \
  f(FD_DataIn8_fineDelay)s \
  f(ePllPhase160MHz)s \
  f(ePllEnablePhase)s \
  f(ePllReferenceFrequency)s \
  f(ePllRes)s \
  f(ePllCap)s \
  f(ePllIcp)s \
  f(RCLK_HYB_en)s \
  f(RCLK_HYB_cur)s \
  f(PRLP_HYB_en)s \
  f(PRLP_HYB_cur)s \
  f(LCBa_HYB_en)s \
  f(LCBa_HYB_cur)s \
  f(BC_HYB_en)s \
  f(BC_HYB_cur)s \
  f(R3L1_out_en)s \
  f(R3L1_out_cur)s \
  f(LCB_out_en)s \
  f(LCB_out_cur)s \
  f(STVclk_out_en)s \
  f(STVclk_out_cur)s \
  f(DataCLK_enable)s \
  f(DataCLK_enpre)s \
  f(DataCLK_cur)s \
  f(Data1_term)s \
  f(Data1_enable)s \
  f(Data1_enpre)s \
  f(Data1_cur)s \
  f(IC_TransSelect)s \
  f(IC_enable)s \
  f(clk_disable_en)s \
  f(prbs_mode)s \
  f(encode_8b10b)s \
  f(encode_cntl)s \
  f(max_Npacket)s \
  f(operating_mode)s \
  f(readout_speed)s \
  f(trigger_mode)s \
  f(clk_disable_sel)s \
  f(clk_disable)s \
  f(efuse_prog_bit)s \
  f(GPO1)s \
  f(GPO0)s \
  f(MaskHPR)s \
  f(BGvdd_cnt_en)s \
  f(BG_RangeLow)s \
  f(BG_setting)s \
  f(BCMM_squelch)s \
  f(BCIDrstDelay)s \
  f(AMAC_SSSH)s \
  f(ABC_ResetB)s \
  f(R3L1_errcount_thr)s \
  f(lcb_errcount_thr)s \
  f(therm_offset)s \
  f(am_ana_set)s \
  f(am_range)s \
  f(am_IntSlope)s \
  f(am_calib)s \
  f(am_enable)
 
#define COMMA_SEP ,
 
#define FLD_LIST(f) FLD_LIST_SEP(f, COMMA_SEP)